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Title:
ANALOG AUTOMATIC EQUALIZING SYSTEM
Document Type and Number:
Japanese Patent JPS5538741
Kind Code:
A
Abstract:

PURPOSE: To realize simplification of the device constitution as well as compensation of the characteristic variation by controlling the equalizer by the control signal obtained by giving the time-division multiplication to the equalizing test signal and then transmitting the signal for comparison with the reference signal.

CONSTITUTION: The signal of equalizing test signal generation circuit 15 of transmission signal processor 1 is applied to transmission signal switch circuit part 14 along with input signals C1 and C2 and then transmitted to transmission line 2 via time axis compression circuit part 16 and signal multiplication circuit part 17. Reception signal processor 3 obtains output signals C10 and C20 via variable equalizing circuit part 32, signal isolation circuit part 33, time axis expansion circuit part 35 and reception signal switch circuit 36 each. Then the detection signal is compared with the reference signal to produce the control signal. Thus part 32 is controlled via equalization control signal memory circuit part 41 to give compensation to the characteristic change of parts 16 and 35.


Inventors:
MAKI KAZUMITSU
HARA HIROYUKI
Application Number:
JP11127378A
Publication Date:
March 18, 1980
Filing Date:
September 12, 1978
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H04B3/04; H04B3/10; H04N17/00; (IPC1-7): H04B3/04



 
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