PURPOSE: To decrease the number of operational amplifiers to one and to reduce circuit scale by connecting a switched capacitor circuit in parallel in order to make a delay time and charging a capacity by shifting by one clock.

CONSTITUTION: When a clock signal 11 is high-level, clock signals 21, 12 and 22 are all low-level (a first timing), at this time, a first type of switches SW11 and SW21 become on, a second type of switches SW31 and SW41 become off, the other terminal of a first capacity C1 is grounded and the first capacity C1 is charged with an impressed voltage. When the clock signal 22 is high-level, the clock signals 11, 21 and 12 are all low-level (a second timing), at this time, the first type of switches SW11 and SW21 and the second type of switches SW31 and SW41 all become off, the first capacity C1 is completely separated and the charge of the first capacity C1 is held. Thus, the number of operational amplifiers can be decreased to one and the circuit scale can be reduced.