PURPOSE: To accelerate the A/D converting speed by comparing sequentially plural constant currents with bit weighting and an input analog signal and deciding every two most significant bits at the same time in A/D conversion.

CONSTITUTION: An SAR (sequential comparison register) 44 controls current switches 46 and 47 so that the switch 46 is thrown to all of the A positions, i.e., 000000 and the switch 47 is thrown to all of the B positions, i.e., 111111 as the initial state when a full scale voltage is 10V and 5.7V is applied as the analog input. An output V7 of a current/voltage (I/V) converting circuit 49 is 0V and an output V6 of an I/V converting circuit 48 is 10V. Divided voltages V2∼V4 of a resistor ladder are respectively 10V, 7.5V, 5V, 2.5V and 0V. When comparators 42-1∼42-3 compare the voltages of V2∼V4 with an analog input voltage, the comparator 42-1 outputs an L level and the comparator 42-3 outputs an H level and the result is fed to a decoder 43. The decoder 43 outputs 10 in this case (1st step). After the high-order 2-bit is decided as 10, the high-order bit of current switches 46, 48 is brought into 10, the comparator 42 compares the divided voltage of the resistor ladder again, and its output is fed to the decoder.