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Title:
ANALOG INTEGRATOR OF DIGITAL SYSTEM
Document Type and Number:
Japanese Patent JPH09321625
Kind Code:
A
Abstract:

To reduce an integrated error by averaging received data and preceding received data for each arithmetic period.

An analog signal is sampled for each arithmetic period and the sampled signal is A/D-converted. Every time an arithmetic period timer is set, this value X1 of A/D-converted data is stored in a 1st memory and a preceding value X2 is stored in a 2nd memory (S2, S3), a mean value M of the X1, X2 is calculated (S4), and the obtained mean values M are integrated sequentially to obtain an integrated value S (S5). In the case of integrating the A/D-converted data without any arithmetic operation, let an arithmetic period be T, let a preceding value be A, and let this value be A+d, then the integrated preceding value is T.A, and the integrated this value is T.A+T.d, which is a stepwise value and an error is produced. However, the averaged value of the integrated this value M is T.A+T.d/2, resulting that the stepwise value is corrected by a slant component T.d/2. Thus, the integrated value S with a small error is obtained by integrating the mean values M sequentially.


Inventors:
SATO MAKOTO
Application Number:
JP13731396A
Publication Date:
December 12, 1997
Filing Date:
May 31, 1996
Export Citation:
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Assignee:
MEIDENSHA ELECTRIC MFG CO LTD
International Classes:
G06J3/00; H03M1/12; (IPC1-7): H03M1/12; G06J3/00
Attorney, Agent or Firm:
志賀 富士弥 (外1名)



 
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