Title:
ANALOG MULTIPLIER
Document Type and Number:
Japanese Patent JP2685715
Kind Code:
B2
Abstract:
PURPOSE: To provide an analog multiplier with little power consumption, small area chip, improved linearity, and high processing speed, and extremely wider range of an input voltage than that of a conventional multiplier using only a bipolar transistor.
CONSTITUTION: This device is provided with a buffering means connected through an output resistance (ROUT) with a positive power source (VDD) so that a multiplied output voltage (V+OUT, V-OUT) can be outputted, which inputs signal values (V+X, V-X) of a multiplier (multiplicand), first - fourth nMOSFET (M1-M4) whose drain terminals are connected with the buffering means, and to whose gate terminals multiplicand (multiplier) signal values (V+Y,V-Y) are inputted and which operates multiplication, and a bias current source (IB) connected with the first - fourth MOSFET (M1-M4), which supplies bias currents.
Inventors:
Hadon Soki
Kim Yong Hwan
Kim Yong Hwan
Application Number:
JP17720694A
Publication Date:
December 03, 1997
Filing Date:
July 28, 1994
Export Citation:
Assignee:
Korea Telecommunications Authority
International Classes:
G06G7/16; G06G7/163; (IPC1-7): G06G7/163
Domestic Patent References:
| JP4106677A |
Attorney, Agent or Firm:
Yoshikazu Tani (1 person outside)
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