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Title:
ANALOG MULTIPLIER
Document Type and Number:
Japanese Patent JPH0333989
Kind Code:
A
Abstract:

PURPOSE: To enable operation with a low voltage source by inputting the output current of a transformer conductance amplifier, which is equipped with differential paired inputs by an NPN transistor, through a current mirror circuit to a multiplier.

CONSTITUTION: NPN transistors TRQ1-Q4 in 9 multiplication block constitute the upper step part of a gilbert multiplier and TRQ5 and Q6 constitute the lower step part. The TRQ5 and Q6 to respectively determine bias currents for the differential pairs of the TRQ1 and Q2 and of the TRQ3 and Q4 are connected through the current mirror circuit, which is composed of the TRQ7 and Q8, to the transformer conductance amplifier composed of TRQ9 and Q10. A current to be generated by a constant current source IQ1 is distributed to the respective parts of the differential pairs by the current mirror circuit, which is composed of TRQ15 and Q16 and a PNP TRQ4, and becomes the bias current of a differential circuit. Thus, by controlling the current with the conductance amplifier for the control of the lower step part in the multiplier, the operation can be executed by the low voltage source such as 1V, for example.


Inventors:
YOSHIZAWA SHIGEO
Application Number:
JP16944489A
Publication Date:
February 14, 1991
Filing Date:
June 29, 1989
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06G7/163; (IPC1-7): G06G7/163
Domestic Patent References:
JPS56162176A1981-12-12
Attorney, Agent or Firm:
Naoki Kyomoto