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Patent Searching and Data


Title:
ANALOG-TO-DIGITAL CONVERTER
Document Type and Number:
Japanese Patent JPS5824233
Kind Code:
A
Abstract:

PURPOSE: To prevent a breakdown due to an in-phase noise applied to an input, by dividing the winding of the insulating transformer of a scanner circuit into two and connecting them to sources of two FETs, and also connecting drains of the FETs mutually.

CONSTITUTION: Two-wire bipolar analog input signals of plural channels CH are A/D-converted by the insulating transformer T2 and FETs X1 and X2 of a scanner circuit provided for each CH. The primary winding of the transformer T2 is divided into two and connected to sources of the FETs X1 and X2, and drains of the X1 and X2 are connected mutually to constitute a series circuit. Insulating transformers T11 and T12 to be supplied with turning-on pulse inputs are provided between the sources and gates of the FETs X1 and X2. Consequently, the FETs are connected together at the drains while neither earth electrostatic capacity wherein electrostatic charges are accumulated nor conductor volume is provided between them except wiring, so the simple constitution prevents the breakdown of FETs due to an in-phase noise.


Inventors:
ISOZAKI MAKOTO
SAITOU SEIICHI
Application Number:
JP11893782A
Publication Date:
February 14, 1983
Filing Date:
July 08, 1982
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H03K17/16; H03K17/693; H03M1/08; H03M1/12; (IPC1-7): H03K13/02
Attorney, Agent or Firm:
Shinichi Kusano