Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
ANALYSIS IDDQ TEST MODULE AND IDDQ TEST METHOD
Document Type and Number:
Japanese Patent JP2010181261
Kind Code:
A
Abstract:

To provide a means capable of performing high-precision measurement and relatively large data processing (analysis) at a high-speed by making a measurement means and an analysis means as a BOST, and reducing the test time.

A mean value processing continuous sampling circuit 202 is provided in an analysis IDDQ test module 200. Once a trigger signal is input to the mean value processing continuous sampling circuit 202 from a semiconductor test device 100, the mean value processing continuous sampling circuit 202 causes an IDDQ measurement part 201 to execute the IDDQ measurement repeated by a prescribed number of times. The value of the IDDQ during measurement is AD converted by a high-precision ADC 203 and sent to a module control part. The module control part stores data which can be used by a data analysis part 207 or the like into a shared data storage part 206.


Inventors:
HANAI HISAYOSHI
Application Number:
JP2009024684A
Publication Date:
August 19, 2010
Filing Date:
February 05, 2009
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
RENESAS ELECTRONICS CORP
International Classes:
G01R31/26; G01R31/28
Domestic Patent References:
JP2000258490A2000-09-22
JP2006119101A2006-05-11
JPH11260872A1999-09-24
JP2002323546A2002-11-08
JP2000088914A2000-03-31
Foreign References:
WO2007049331A12007-05-03
Attorney, Agent or Firm:
Yamato Tsutsui