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Patent Searching and Data


Title:
ANALYZING METHOD FOR RESIN SEALED INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH03110488
Kind Code:
A
Abstract:

PURPOSE: To make observation of the inside easy and to enhance reliability of analytic technique for trouble of an integrated circuit by exposing the whole face of chips of the integrated circuit sealed with resin while leaving the lead part residual.

CONSTITUTION: The external derivative wires 3 are fixed to a base (ceramic package) 4 for fixing a sample with solder as shown in a figure. The sample prepared in such a way is immersed in an acidic resin solvent to remove resin. Thereby observation of the inside which is difficult heretofore can be surely and quickly performed even in an integrated circuit thin in thickness of sealed resin. Reliability of analytic technique for trouble of the integrated circuit is enhanced.


Inventors:
NOGUCHI TAKAYUKI
Application Number:
JP24815789A
Publication Date:
May 10, 1991
Filing Date:
September 26, 1989
Export Citation:
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Assignee:
MATSUSHITA ELECTRONICS CORP
International Classes:
H01L21/66; G01R31/26; (IPC1-7): G01R31/26; H01L21/66
Attorney, Agent or Firm:
Koji Hoshino