PURPOSE: To obtain a data highway system with high efficiency, by comparing the priority of a packet with that of a sub-system, and using the said idle packet when the priority of the said sub-system is larger or both the priorities are equal.

CONSTITUTION: A data synchronism detecting circuit 11 detects the synchronizing flag of a frame header arriving at each prescribed period. When an arrival packet is in use and the addressed address and the address of a sub-system address set circuit 14 are compared at a comparison circuit 16, a common control circuit 18 writes the data content of the arrival packet to a receiving buffer memory 20. When a data is stored in the receiving buffer memory 20, the channel control circuit transmits the data to a sub-system 24 via a drive circuit 22. A response circuit 13 writes the receiving state to a response section in the packet with the indication of the common control circuit 18 and a channel control circuit 19.