Title:
フラッシュメモリデバイスのためのハッキング防止メカニズム
Document Type and Number:
Japanese Patent JP7195311
Kind Code:
B2
Abstract:
Multiple embodiments are disclosed for enhancing security and preventing hacking of a flash memory device. The embodiments prevent malicious actors from hacking a flash memory chip to obtain data that is stored within the chip. The embodiments include the use of fault detection circuits, address scrambling, dummy arrays, password protection, improved manufacturing techniques, and other mechanisms.
Inventors:
Tran, Huban
Tiwari, bipin
Doe, Nan
Tiwari, bipin
Doe, Nan
Application Number:
JP2020520547A
Publication Date:
December 23, 2022
Filing Date:
September 22, 2018
Export Citation:
Assignee:
SILICON STORAGE TECHNOLOGY, INC.
International Classes:
G11C16/22; G06F21/74; G06F21/79
Domestic Patent References:
| JP2003298569A | ||||
| JP2015026408A | ||||
| JP2006509287A |
Foreign References:
| US20170147509 |
Attorney, Agent or Firm:
Patent Attorney Corporation Wisdom International Patent and Trademark Office
Previous Patent: Method for manufacturing inliner lined pipe
Next Patent: PRESSURE-CLAMPING METHOD OF SYNTHETIC RESIN LIQUID-IMPREGNATED WOOD
Next Patent: PRESSURE-CLAMPING METHOD OF SYNTHETIC RESIN LIQUID-IMPREGNATED WOOD