Title:
APPARATUS FOR AVOIDING PIEZOELECTRIC EFFECT CREATED IN ELECTRIC ELIC ELEMENT IN SEMICONDUCTOR MATERIAL AND ITS FORMING
Document Type and Number:
Japanese Patent JPH01313979
Kind Code:
A
Abstract:
PURPOSE: To eliminate the minus influence of piezo effect due to mounting, by providing a gap between the part of the electrical element of a semiconductor material where the electrical element for generating piezo effect only partially is formed and a support material. CONSTITUTION: A gap 4 is provided between the part of an electrical element 3 of a semiconductor material 1 where the electrical element 3 for generating piezo effect only partially is formed and a support material 2. Therefore, since various kinds of elements of an integrated circuit are insulated electrically and completely, no minus influence is generated in the function even if the electrical insulation of various kinds of elements is not sufficient, thus eliminating the minus influence of piezo effect due to mounting, especially the minus influence to the accuracy and long-term stability of an electronic precision circuit formed by a semiconductor element.
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Inventors:
BIITO HEERUKU
RADEIFUOE POPOBUITSUKU
RADEIFUOE POPOBUITSUKU
Application Number:
JP9770989A
Publication Date:
December 19, 1989
Filing Date:
April 19, 1989
Export Citation:
Assignee:
LANDIS & GYR AG
International Classes:
H01L41/02; G01L9/00; H01L43/04; (IPC1-7): H01L41/02
Attorney, Agent or Firm:
Taku Kato
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