APPARATUS FOR BAKING RESIST ON SEMICONDUCTOR WAFER

Title:

APPARATUS FOR BAKING RESIST ON SEMICONDUCTOR WAFER

Document Type and Number:

Japanese Patent JP3971050

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To provide an apparatus for backing a resist on a semiconductor wafer.
SOLUTION: This apparatus 30 for baking a resist on a semiconductor wafer 18 comprises a base 10 for placing the wafer 18, a cover 12 having the base 10 and a boundary surface to couple/separate the base 10 on the boundary surface, and a means for controlling the temperature of the boundary surface circumferential air of the base 10 and the cover 12. Thus, at the performing of a baking step, air of a predetermined temperature controlled by the means is introduced into the space having the wafer 18 disposed therein.

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Inventors:

Zhao Shun Jie

Application Number:

JP12301099A

Publication Date:

September 05, 2007

Filing Date:

April 28, 1999

Export Citation:

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Assignee:

Samsung Electronics Co.,Ltd.

International Classes:

H01L21/027; F27D7/06; G03F7/38; H01L21/00; (IPC1-7): H01L21/027; G03F7/38

Domestic Patent References:

JP6275512A
JP10055951A
JP4158512A
JP7254557A
JP62069613A

Attorney, Agent or Firm:

Masatake Shiga
Takashi Watanabe

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