PURPOSE: To enable high resolving capacity sampling over an entire detection range without increasing memory capacity, by taking in a receiving wave signal in a predetermined cycle while equally dividing the predetermined cycle interval into plural sections to also take in the information at the point of time when a signal level is changed.

CONSTITUTION: Ultrasonic wave receiving and detecting output is sampled by an A/D converter 6 controlled by a frequency dividing clock and, when the comparison result with the immediate-before sampling value coincides, a comparator 10 generates high level output to bring latch circuits 11, 14 to a latch state through an AND gate 12. In this case, the sampling value changed in the level thereof and the change point of time due to a counter 13 for counting frequency dividing output are respectively temporarily stored in buffers 15, 16 through the circuits 11, 14. On the other hand, plural predetermined numbers of sampling values at every predetermined cycle of the frequency dividing clock are temporarily stored in the buffer 15 regardless of the presence and absence of change. By this constitution, the contents of the buffers 15, 16 are written in memory 18 and display over an entire detection range based on a high resolving capacity sampling value is performed corresponding to the reading of the memory 18 without increasing the memory capacity of the memory 18.