Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
APPARATUS FOR FLATTENING SEMICONDUCTOR SUBSTRATE, AND TEMPORARY DISPLACEMENT SURFACE PLATE USED FOR THE SAME
Document Type and Number:
Japanese Patent JP2011155095
Kind Code:
A
Abstract:

To provide a flattening apparatus that grinds and polishes the backside of a semiconductor substrate at high throughput to thin and flatten the substrate and manufactures the semiconductor substrate with less contamination sticking thereto, and to provide a temporary placement surface plate used for the flattening apparatus.

The flattening apparatus 1 includes a loading/unloading stage chamber 11a for the semiconductor device, a backside polishing stage chamber 11c, and a backside grinding stage chamber 11b, each stage chamber housing each mechanical element. The flattening apparatus 1 is so designed that a backside polishing stage 70 capable of polishing two substrates at the same time achieves a throughput time twice as high as a throughput time of a backside polishing stage 20 polishing one substrate at a time.


Inventors:
MOCHIMARU YORIYUKI
ABE SUMUTO
Application Number:
JP2010015044A
Publication Date:
August 11, 2011
Filing Date:
January 27, 2010
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
OKAMOTO MACHINE TOOL WORKS
International Classes:
H01L21/304; B24B37/04; B24B37/10