To provide a layout design apparatus capable of designing a semiconductor integrated circuit so that a chip size becomes small.

The layout design apparatus includes: a timing analysis unit 103 for performing timing analysis based on a net list and delay information; an adjustment target extraction unit 104 which, when a timing error is generated in the timing analysis, extracts an adjustment target cell related to the timing error; a reinforcing fill cell library 105 for storing a plurality of reinforcing fill cells in each of which a first cell frame is a boundary of the adjustment target cell and a first diffusion area exists on the outside of a second cell frame; and a cell replacement unit 106 for extracting the first reinforcing fill cell of which the second cell frame is respective boundaries of the plurality of reinforcing fill cells and which has the same size as a normal fill cell adjacent to the adjustment target cell from the plurality of reinforcing fill cells, replacing the normal fill cell with the first reinforcing fill cell so that the first cell frame and the second cell frame are adjacently arranged and connecting a transistor to the first diffusion area.