To provide an apparatus for stopping a motor capable of stopping the motor without contacting with a stopper when a CPU runs away.

Output signals of an upper limit switch 33, a lower limit switch 24 and a watch dog timer 102 are input to a 3-input OR circuit 105. A control pulse signal output from a motor controller 66 and an output signal of the OR circuit 105 are input to a 2-input OR circuit 106. If the timer 102 is time up due to runaway or the like of the CPU so that its output signal becomes an H level, or if the switch 34 is operated so that its output signal becomes an H level, an output from the OR circuit 105 becomes the H level. Thus, a control pulse signal is cut off by the OR circuit 106, a drive signal is not input to the motor 21, and hence the motor 21 is stopped in emergency.