To realize an intersection thin film memory structure for suppressing a leakage or a crosstalk of a current between memory cells to a minimum limit and to realize a process for manufacturing the same.
An intersection memory array having a plurality of memory arrays is manufactured on a substrate (85). Each memory array has a diode and an anti-fuse. First and second conductive materials are disposed on individual strips on the substrate, and a plurality of first and second perpendicularly crossing electrodes (93, 90) having intersections are formed. A plurality of semiconductor layers (87, 88, and 89) are disposed between the first and second electrodes (93, 90), and a plurality of diodes (81) are formed between the intersections of the electrodes. A passivation layer (86) is disposed between the first electrode (93) and a diode (81), and a plurality of the anti-fuses (82) adjacent to the diode (81) are formed. A part of the diode layers (87, 88, and 89) between the intersections is removed, a plurality of memory cells (91) having a trench (92) of a row are formed between the adjacent memory cells (91), and a barrier against the crosstalk is provided.
TAUSSIG CARL P
BECK PATRICIA A
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