Title:
I/O ARCHITECTURE FOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2001345387
Kind Code:
A
Abstract:
To provide a structure and method capable of effectively laying out elements of an integrated circuit.
This embodiment has an integrated circuit containing a plurality of I/O modules. The I/O module has a bond pad formed on a substrate. The I/O module has a static charge discharging device formed in the substrate. The static charge discharging device is at least partially formed under the bond pad. The I/O module has an I/O buffer formed in the substrate. The I/O buffer is connected to the bond pad. A communication between the bond pad and a circuit formed in the substrate can be obtained by the I/O buffer. The circuit is laid out substantially adjacent both the static charge discharging device and the I/O buffer.
Inventors:
KO U-MING
Application Number:
JP2001003952A
Publication Date:
December 14, 2001
Filing Date:
January 11, 2001
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
H01L27/04; H01L21/82; H01L21/822; (IPC1-7): H01L21/82; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Akira Asamura (3 outside)