Title:
演算回路
Document Type and Number:
Japanese Patent JP7381426
Kind Code:
B2
Abstract:
To embody optimization in sum operation.SOLUTION: An arithmetic circuit comprises a first processing circuit, a second processing circuit, an addition circuit, and a saturation arithmetic circuit. The first processing circuit, in which blocks for each prescribed number of digits are used, divides one input term so that the lowest bit for each block superimposes the highest bit in a neighboring lower block, and calculates a partial product for each block and another input term, based on Booth Recoding for controlling codes when the Booth Recoding becomes ±0. The second processing circuit simplifies the partial product. The addition circuit outputs a simplified result and a sum of addition numbers. A saturation logic circuit executes saturation processing based on the result outputted by the second processing circuit, and the result outputted by the addition circuit.SELECTED DRAWING: Figure 1
Inventors:
Nama Tenmoku Tatsuya
Application Number:
JP2020154022A
Publication Date:
November 15, 2023
Filing Date:
September 14, 2020
Export Citation:
Assignee:
Toshiba Corporation
Toshiba Electronic Devices & Storage Corporation
Toshiba Electronic Devices & Storage Corporation
International Classes:
G06F7/533; G06F7/503; G06F17/10
Domestic Patent References:
| JP2008527465A | ||||
| JP2016045685A | ||||
| JP2014209347A | ||||
| JP61062937A | ||||
| JP11126157A | ||||
| JP2011248904A | ||||
| JP1267728A | ||||
| JP2009271598A |
Foreign References:
| US20090013022 | ||||
| US20050080834 |
Attorney, Agent or Firm:
Yukitaka Nakamura
Satoru Asakura
Takeshi Sekine
Akira Akaoka
Nobuto Ishihara
Satoru Asakura
Takeshi Sekine
Akira Akaoka
Nobuto Ishihara
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