Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
ARITHMETIC CIRCUIT
Document Type and Number:
Japanese Patent JPS60176182
Kind Code:
A
Abstract:

PURPOSE: To enable an arithmetic circuit to be used as a multiplier circuit and a divider circuit by feeding back the output of a differential amplifier whose one input terminal is supplied by ≥2 signals together with another signal which is supplied to the other input terminal.

CONSTITUTION: The 1st current source I2 and the 2nd current source I4 are logarithm-converted by a transistor Q7 and a transistor Q8, respectively, added to the base of one transistor Q11 of a differential amplifier and inputted. On the other hand, the 3rd current source I3 is impressed to the base of a transistor Q10 at the next stage as logarithm-converted voltage by the transistor Q8. The voltage is added to the voltage obtained by logarithm-converting a collector current of a transistor Q14 at the 1st output side of a current mirror circuit by the transistor Q10, and supplied to the base of other transistor Q12 of the differential amplifier. Both input voltages attain to differential inputs of said amplifier, and by a transmission characteristic due to inverse-logarithm conversion of said amplifier, they are introduced to a collector of the transistor Q12 as a current of an exponential function.


Inventors:
HAGINO HIDEYUKI
Application Number:
JP3017584A
Publication Date:
September 10, 1985
Filing Date:
February 22, 1984
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
TOSHIBA KK
International Classes:
H03C1/54; G06G7/16; G06G7/163; H03D1/22; H03D7/12; (IPC1-7): H03C1/54; H03D1/22; H03D7/12
Attorney, Agent or Firm:
Noriyuki Noriyuki



 
Previous Patent: PICTURE DATA COMPRESSION SYSTEM

Next Patent: JPS60176183