Title:
ARITHMETIC CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS553045
Kind Code:
A
Abstract:
PURPOSE: To increase the arithmetic process efficiency by providing the memory element to be presented for the operation also outside the microprocessor.
CONSTITUTION: The output of multiplexers 35 and 32 are supplied to register 100 through multiplexer 110, and thus the data to be set to accumulator 10 can be all supplied to register 100. In other words, the control is possible so that an agreement may always be obtained for the contents between register 100 and accumulator 10. Under such conditions, in case the operation is given to the contents of accumulator 10 via the arithmetic unit provided outside microcomputer 1, register 100 can be used in place of accumulator 10. And this switching is performed through multiplexer 32.
Inventors:
KITAMURA SHIYUNJI
SATOU FUMITAKA
HASHIMOTO YASUICHI
SATOU FUMITAKA
HASHIMOTO YASUICHI
Application Number:
JP7520578A
Publication Date:
January 10, 1980
Filing Date:
June 21, 1978
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G06F7/00; (IPC1-7): G06F7/00
Domestic Patent References:
| JPS51107735A | 1976-09-24 |
Next Patent: JPS553046