To provide an arithmetic device capable of arithmetic operation with high accuracy by suppressing the increase of occupation area to a chip, even in an operation in which the result in the middle of the operation exceeds the bit width of a general register.
A plurality of general registers 12 have a first bit width. An arithmetic unit 13 includes first and second input ends, in which at least the first input end has a second bit width wider than the first bit width, and performs operation for data supplied from the general register 12 to the first and the second ends. As a result of the operation by the arithmetic unit 13, a first register and second register ov0, ov1, having a narrower bit width than the first bit width, retain overflowed digit data as overflow data, and supplies the retained overflow data to at least one input end of the arithmetic unit 13 as upper bits.
| JPH07253965A | 1995-10-03 | |||
| JP2002236581A | 2002-08-23 | |||
| JP2004013519A | 2004-01-15 | |||
| JPH05250142A | 1993-09-28 |
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto