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Title:
ARITHMETIC OPERATION UNIT COMPRISING CPU AND PLURAL PU AND FPU
Document Type and Number:
Japanese Patent JPH0744504
Kind Code:
A
Abstract:

PURPOSE: To increase the speed of software implementation in the multiple operation in an OS and to increase the speed of data processing such as three- dimension of graphic processing or over without increasing a clock frequency of a CPU by applying allocation processing to a sub processor and a co- processor by a main processor automatically through the architecture of the unit.

CONSTITUTION: A main processor CPU discriminates as to whether it is operated by a single task or plural tasks. In the case of a single task, a sub processor PU1 is reserved by a control signal CS1 as a software and a processor of data processing. When graphics are processed in the operation of the software, numeral arithmetic processors FPU1-FPUX are allocated for arithmetic operation processing for each of dimension elements x, y, z or the like based on control signals CSF1, 2,...X. On the other hand, in the case of plural tasks, sub processors PU1-PUX are reserved by the control signals 1,2,..., X as processors for the software and data processing.


Inventors:
OKAMOTO KATSUHIKO
Application Number:
JP18503793A
Publication Date:
February 14, 1995
Filing Date:
July 27, 1993
Export Citation:
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Assignee:
HITACHI LTD
HITACHI TOKYO ELECTRONICS
International Classes:
G06F9/38; G06F15/16; (IPC1-7): G06F15/16; G06F9/38
Attorney, Agent or Firm:
Tomio Ohinata