PURPOSE: To increase the speed of software implementation in the multiple operation in an OS and to increase the speed of data processing such as three- dimension of graphic processing or over without increasing a clock frequency of a CPU by applying allocation processing to a sub processor and a co- processor by a main processor automatically through the architecture of the unit.
CONSTITUTION: A main processor CPU discriminates as to whether it is operated by a single task or plural tasks. In the case of a single task, a sub processor PU1 is reserved by a control signal CS1 as a software and a processor of data processing. When graphics are processed in the operation of the software, numeral arithmetic processors FPU1-FPUX are allocated for arithmetic operation processing for each of dimension elements x, y, z or the like based on control signals CSF1, 2,...X. On the other hand, in the case of plural tasks, sub processors PU1-PUX are reserved by the control signals 1,2,..., X as processors for the software and data processing.
JP3731843 | METHOD AND DEVICE FOR EXECUTING INSTRUCTION SEQUENCE |
WO/2003/100599 | ACCESS TO A WIDE MEMORY |
HITACHI TOKYO ELECTRONICS