Title:
ARITHMETIC PROCESS SYNCHRONIZING SYSTEM OF MULTIPLEXED SYSTEM
Document Type and Number:
Japanese Patent JPS58105367
Kind Code:
A
Abstract:
PURPOSE:To enable a retarded operation of an overall system, by providing a transfer means of the synchronous information to ensure the synchronism for an arithmetic process the overall system with synchronizing command given from a nondefective CPU and substituting the CPU for another nondefective system if the CPU has a fault. CONSTITUTION:The multiplexed CPUA-CPUC are connected to the same bus 1, and an input data DI is fetched to each of CPUA-CPUC via input ports IA- IC connected to each CPU as well as a wired OR circuit OR. At the same time, the arithmetic result given from each CPU is applied to a 2-out-of-3 output selecting circuit 2 via output ports OA-OC. Then the arithmetic result DO of a multiplexed system is delivered to outside.
Inventors:
ISHIZAKI JIYUNKO
KIMURA KOUICHI
AOTSU HIROAKI
MOROOKA YASUO
KANZAKI HIDEO
KIMURA KOUICHI
AOTSU HIROAKI
MOROOKA YASUO
KANZAKI HIDEO
Application Number:
JP20352181A
Publication Date:
June 23, 1983
Filing Date:
December 18, 1981
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G06F15/16; G06F11/20; G06F15/177; (IPC1-7): G06F15/16
Attorney, Agent or Firm:
Akio Takahashi