Title:
ARITHMETIC PROCESSING DEVICE AND ARITHMETIC PROCESSING METHOD
Document Type and Number:
Japanese Patent JP2022175420
Kind Code:
A
Abstract:
To output data without access competition even in the case of simultaneously receiving access requests from a plurality of access requesting units.SOLUTION: A plurality of banks have a first cache area including a first entry, a second cache area including a second entry, a cache control unit and a hit error determination unit. The cache control unit stores data read from a storage device in response to a plurality of access requests in one first entry and one second entry in the case that the plurality of access requests simultaneously received from a plurality of request issuing units undergo a cache error. The cache control unit outputs data included in the first entry undergoing the cache hit and data included in the second entry undergoing the cache hit to issuing sources of the plurality of access requests in the case that the plurality of access requests simultaneously received from the plurality of request issuing units undergo the cache hit in the first cache area and the second cache area.SELECTED DRAWING: Figure 5
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Inventors:
YODA KATSUHIRO
Application Number:
JP2021081786A
Publication Date:
November 25, 2022
Filing Date:
May 13, 2021
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G06F12/0846
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Tadahiko Ito
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