Title:
演算処理システム、特に通信装置のための演算処理システム
Document Type and Number:
Japanese Patent JP3651672
Kind Code:
B2
Abstract:
The invention relates to a processor system which is configured as a communications controller and which comprises a central processor unit ( 1 ) for executing instructions filed in a program memory ( 8 ), whereby the processor unit ( 1 ) comprises only one path ( 2,3 ) for reading out an instruction from the program memory ( 8 ) and for decoding the instruction. In addition, several parallelly operable execution paths ( 4,5;6,7 ) for parallelly executing different program flows are provided which each access the path ( 2,3 ) jointly used for reading out and decoding an instruction.
Inventors:
Knee, shaoning
Application Number:
JP2001528795A
Publication Date:
May 25, 2005
Filing Date:
October 05, 2000
Export Citation:
Assignee:
Infineon Technologies AG
International Classes:
G06F9/30; G06F9/38; (IPC1-7): G06F9/38
Domestic Patent References:
| JP6324868A |
Foreign References:
| WO1997014093A1 |
Attorney, Agent or Firm:
Kenzo Hara
Ryuichi Kijima
Toru Enya
Ichiro Kaneko
Ryuichi Kijima
Toru Enya
Ichiro Kaneko
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