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Title:
ARITHMETIC UNIT, IMAGE PROCESSING APPARATUS, AND DATA PROCESSING APPARATUS
Document Type and Number:
Japanese Patent JP2007323308
Kind Code:
A
Abstract:

To execute arithmetic operation according to a plurality of instructions more rapidly than a conventional method, even if it is a case where a single-instruction/multi-data type microprocessor is used.

A cluster 11-2 receives a Valid signal from a cluster 11-1, while receiving either of pixel data showing text pixels or pixel data showing image pixels sequentially. Since pixel data corresponding to an H level Valid signal is a text pixel, the cluster 11-2 applies edge enhancement processing to this pixel data. On the other hand, since pixel data corresponding to an L level Valid signal is an image pixel, the cluster 11-2 does not perform edge emphasis processing to this pixel data. A cluster 11-3, while applying gradation enhancement processing to pixel data corresponding to the H level Valid signal, does not apply gradation enhancement processing to pixel data corresponding to the L level Valid signal.

COPYRIGHT: (C)2008,JPO&INPIT


Inventors:
YAMADA KAZUO
Application Number:
JP2006152050A
Publication Date:
December 13, 2007
Filing Date:
May 31, 2006
Export Citation:
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Assignee:
FUJI XEROX CO LTD
International Classes:
G06F15/80; G06T1/20
Domestic Patent References:
JPH06259391A1994-09-16
JP2003330570A2003-11-21
JPH09106389A1997-04-22
JPH11345218A1999-12-14
Attorney, Agent or Firm:
川▲崎▼ 研二