To execute arithmetic operation according to a plurality of instructions more rapidly than a conventional method, even if it is a case where a single-instruction/multi-data type microprocessor is used.
A cluster 11-2 receives a Valid signal from a cluster 11-1, while receiving either of pixel data showing text pixels or pixel data showing image pixels sequentially. Since pixel data corresponding to an H level Valid signal is a text pixel, the cluster 11-2 applies edge enhancement processing to this pixel data. On the other hand, since pixel data corresponding to an L level Valid signal is an image pixel, the cluster 11-2 does not perform edge emphasis processing to this pixel data. A cluster 11-3, while applying gradation enhancement processing to pixel data corresponding to the H level Valid signal, does not apply gradation enhancement processing to pixel data corresponding to the L level Valid signal.
COPYRIGHT: (C)2008,JPO&INPIT
JPH06259391A | 1994-09-16 | |||
JP2003330570A | 2003-11-21 | |||
JPH09106389A | 1997-04-22 | |||
JPH11345218A | 1999-12-14 |
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