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Patent Searching and Data


Title:
ARITHMETIC UNIT AND ARITHMETIC METHOD
Document Type and Number:
Japanese Patent JP2004227248
Kind Code:
A
Abstract:

To quickly execute a remainder arithmetic operation and a multiplication remainder arithmetic operation or the like.

An arithmetic unit 1 performs a sum of products arithmetic operation by a Montgomery method. A booth encoding part 20 divides a multiplier Y constituted of a plurality of bits by every two bits, and booth-encodes any value of 0, 1, 2, and 3 of the divided 2 bits into any of -2, -1, 0, 1 and 2. A partial product generating part 400 multiplies the booth-encoded multiplier Y and a multiplicand X to generate a plurality of partial product columns having the value of any of -2X, -X, 0, X and 2X. A partial product adding part 450 operates the padding of the code bits of the plurality of partial product columns to line up the bit positions of the code bits, and sets predetermined constant bits according to predetermined conditions to extend codes, and preliminarily calculates a constant value, and adds the constant value to the addition result of the addition of the plurality of partial product columns, and outputs it as the multiplication result of the multiplier Y and the multiplicand X.


Inventors:
SUZUKI DAISUKE
Application Number:
JP2003013780A
Publication Date:
August 12, 2004
Filing Date:
January 22, 2003
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06F7/72; G09C1/00; G06F7/533; (IPC1-7): G06F7/72; G09C1/00
Attorney, Agent or Firm:
Shoji Mizoi
Keiko Hada
Sanmei Takeuchi
Hiroto Yamachi