To provide an arithmetic unit with a small-scale circuit and capable of high-speed operations.

The arithmetic unit is provided with a first parallel/serial conversion circuit which divides first parallel data into a prescribed numbers of first partial data, each composed of a prescribed numbers of bit and sequentially provides the prescribed numbers of first partial data one by one, and a second parallel/serial conversion circuit which divides a second parallel data into a prescribed numbers of second partial data, each composed of a prescribed numbers of bits and sequentially provides the prescribed numbers of second partial data one by one. Also the device includes a serial computing unit which sequentially executes operations for the prescribed numbers of first partial data provided sequentially and the prescribed numbers of second partial data sequentially provided for each partial data for a prescribed portions, and a serial/parallel conversion circuit which sequentially receives and integrates the result of the mathematical operation of the operational circuit for the prescribed minutes, and then outputs it as third parallel data.