Title:
ARRANGEMENT FOR MEASURING AND ELIMINATING BIAS DISTORTION
Document Type and Number:
Japanese Patent JPH0221751
Kind Code:
A
Abstract:
PURPOSE: To correct bias distortion for a binary signal in a type which does not include zero frequency spectrum components at all by constituting a counting means of a distortion measuring circuit and a correction counting means. CONSTITUTION: A counting means is constituted of a distortion measuring circuit DM and a correction counting circuit UDC. The distortion measuring circuit DM is constituted of a binary counter for analyzing a signal at the rate of a sampling frequency in a prescribe measuring period, and judging the code of the distortion, and the correction counting circuit UDC is constituted of an up-down counter, and the code and quantized value of bias distortion are outputted. A data signal from the correction counting circuit UDC is transmitted to the output terminal O of an arrangement BDC, and also transmitted to the input of the distortion measuring circuit DM, and analyzed there. The code of the distortion is detected in a correcting circuit CC from signals DSQ and the inverse of DSQ outputted by the correction counter UDC. Thus, a signal having distortion can be corrected by lengthening '1' or '0' according to the code of the distortion by a single stabilizing circuit VOS.
Inventors:
JIERAARU PUUZUURI
Application Number:
JP9051789A
Publication Date:
January 24, 1990
Filing Date:
April 10, 1989
Export Citation:
Assignee:
TRT TELECOM RADIO ELECTR
International Classes:
H04L12/26; H04L25/06; H04L25/02; (IPC1-7): H04L25/02; H04L25/06
Attorney, Agent or Firm:
Tadahiko Ito (2 outside)
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