Title:
ARRANGEMENT AND WIRING METHOD FOR SCAN TEST CIRCUIT AND ARRANGEMENT AND WIRING DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3013332
Kind Code:
B2
Abstract:
PURPOSE: To prevent mis-latching due to clock skew by arranging circuit elements of a scan test circuit and implementing the processing avoiding malfunction due to a clock skew after rough wiring.
CONSTITUTION: A flip-flop 105 is controlled by an opposit phase of 2nd clock ck12 and set to be an erroneous element by prescribed control and arranged to a scan test circuit. Then, wiring processing for scan signal lines 131 to 136 connecting flip-flop circuits 101 to 105 in the sequence shown in figure is executed. That is, a scan chain is formed by connecting the flip-flop circuits 101 to 105 in series with the scan signal lines 131 to 136. Data in normal operation are propagated through data signal lines 141 to 148 connecting combination circuits 150 to 153 to the flip-flop circuits 101 to 105.
Inventors:
Hisato Yoshida
Joji Katsuren
Tetsuro Yoshimoto
Masahiro Fukui
Tadahiro Yoshida
Joji Katsuren
Tetsuro Yoshimoto
Masahiro Fukui
Tadahiro Yoshida
Application Number:
JP2144594A
Publication Date:
February 28, 2000
Filing Date:
February 18, 1994
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F17/50; H01L21/66; H01L21/82; H01L21/822; G01R31/28; H01L27/04; (IPC1-7): G06F17/50; G01R31/28; H01L21/82
Domestic Patent References:
| JP4172267A | ||||
| JP346821A | ||||
| JP2236779A | ||||
| JP5151311A |
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)