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Title:
ARRAY SUBSTRATE INSPECTION METHOD
Document Type and Number:
Japanese Patent JP2008292582
Kind Code:
A
Abstract:

To provide a defect detection method capable of precisely detecting a defect of an array substrate.

In an array substrate inspection method, wherein auxiliary capacitance wiring 18 connected to a picture element electrode 12 via an auxiliary capacitance Cs and signal wiring 16 supplying a signal voltage Vs to the picture element electrode 12 are provided so as to cross each other via an insulating layer 22 on the array substrate 1 in which multitude of the picture element electrodes 12 are arranged in a matrix, an auxiliary capacitance voltage Vcs is applied to the auxiliary capacitance wiring 18, and the signal voltage Vs is applied to the signal wiring 16 so that the defect of the array substrate 1 is detected on the basis of the voltage Vp generated in the picture element electrode 12, a potential difference between the signal voltage Vs and the auxiliary capacitance voltage Vcs is increased stepwisely.


Inventors:
IIDA TAKESUKE
Application Number:
JP2007135821A
Publication Date:
December 04, 2008
Filing Date:
May 22, 2007
Export Citation:
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Assignee:
SHARP KK
International Classes:
G02F1/13; G02F1/1368; G09F9/00; G09G3/20; G09G3/36
Attorney, Agent or Firm:
Noboru Ueno