To provide a compact array of a floating gate nonvolatile memory cell without contact points and isolation, and to provide its manufacturing method and its operation mode.
An array of a floating gate nonvolatile memory cell without a contact point and an isolation has a plurality of memory cells (112), each having a floating gate (22) for storing a charge arrayed in many rows and columns on a semiconductor substrate (50). All bit lines (16) and source lines (20) are embedded, having no contact point. In the first embodiment, each cell is represented by a transistor having laminate of a transistor gate (14) and a control gate (24) connected to another auxiliary transistor. All arrays may be formed into a planar shape, or preferably, each floating gate transistor is located inside a trench (58), or each auxiliary transistor is located inside a trench.
TRAN HIEU VAN
FRAYER JACK
Fumiaki Otsuka
Toshio Imajo
Takaki Nishijima
Next Patent: CIRCUIT CARRIER AND STRUCTURE ELEMENT FOR SEMICONDUCTOR CHIP