Title:
ASK IDENTIFICATION DETERMINATION CIRCUIT, RECEPTION DEVICE, AND PROCESSOR
Document Type and Number:
Japanese Patent JP2014241540
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To realize demodulation of a digital signal from an ASK multi-value signal at low latency.SOLUTION: An ASK identification determination circuit 100 includes: an upper bit determination block 111 for identifying an upper bit value using one identification point for amplitude of an ASK signal; an upper bit superimposing block 121 for accepting a blanch input of the ASK signal, and deriving an absolute difference signal relative to the center of the amplitude for the ASK signal by superimposing the ASK signals; an inversion block 122 for controlling inverting or not inverting the absolute difference signal derived by the upper bit superimposing block 121 according to an identification result by the upper bit determination block 111; a lower bit determination block 123 for identifying a lower bit value using one identification point for signal amplitude outputted by the inversion block 122; and an output buffer 103 for outputting identification results by the upper bit determination block 111 and the lower bit determination block 123 by synchronizing with a clock.
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Inventors:
SHIMIZU TAKASHI
MATSUI JUN
YAMAMOTO TAKESHI
MATSUI JUN
YAMAMOTO TAKESHI
Application Number:
JP2013123765A
Publication Date:
December 25, 2014
Filing Date:
June 12, 2013
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H04L25/49; H03M5/20; H04L25/03; H04L27/02
Domestic Patent References:
| JPH04346520A | 1992-12-02 | |||
| JP2001077870A | 2001-03-23 | |||
| JPH08237314A | 1996-09-13 |
Attorney, Agent or Firm:
Akinori Sakai