Title:
ASSOCIATIVE MEMORY SYSTEM
Document Type and Number:
Japanese Patent JPS56152045
Kind Code:
A
Abstract:
An associative memory system for a relational data base comprises hardware circuits which permit a variety of operations to be carried out on data, including modification of data. The circuits include a first means (328) and a second means (320, 322, 324, 326) for simultaneously receiving a stream of data bytes from a storing means (310), the second means carrying out selected operations on the data stream. The first means (328) includes a loop buffer for storing K bytes of the data stream and modified data received from the second means. The first means (328) also includes means for selectively rewriting data back to its original location in the storing means at the same time as data is read from the storing means, whereby a write address is obtained by subtracting K from the current read address. The storing means is arranged as blocks of storage elements, preferably CCD arrays, arranged such that K bytes of data are obtained from a first block followed by K bytes of data from a second block. Preferably a plurality of associative data controllers are provided each data controller including a first means (328) and a second means (320, 322, 324, 326). The storing means (310) is divided into a plurality of arrays of blocks of data, with each array being coupled to a respective data controller, thus enabling the data controllers to operate simultaneously on the arrays.
Inventors:
JIYON UEIN SUCHIYUUATO
DARARU UEIN BURUKU
MAABUIN REI DEIFUORISUTO
DARARU UEIN BURUKU
MAABUIN REI DEIFUORISUTO
Application Number:
JP4570181A
Publication Date:
November 25, 1981
Filing Date:
March 30, 1981
Export Citation:
Assignee:
NCR CO
International Classes:
G11C15/00; G06F17/30; G11C15/04; (IPC1-7): G06F7/22; G06F15/40; G11C15/00