Title:
連想メモリ
Document Type and Number:
Japanese Patent JP4298104
Kind Code:
B2
Abstract:
An associative memory includes an array of CAM cells each having a transistor indicating a result from comparing a stored bit with a reference bit. The transistors are connected in serial in each row of the array to form a NAND circuit producing a signal representing that the bits stored in all the cells in the row are consistent with the reference bits or otherwise that the cell at the LSB of the row stores a bit consistent with a reference bit. Each column of the array includes a logic circuit for masking the bits except those continuous from the MSB toward the LSB which correspond to the bits of a word having the most bits continuous from the MSB toward the LSB and consistent with the bits of the reference word among the stored words. The NAND circuit in a row of the cells storing a word having the most bits continuous from the MSB toward the LSB and consistent with the corresponding bits of a reference word develops a signal representing the longest coincidence data detected.
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Inventors:
Tokuaki Takahashi
Hideaki Odagiri
Hideaki Odagiri
Application Number:
JP2000008714A
Publication Date:
July 15, 2009
Filing Date:
January 18, 2000
Export Citation:
Assignee:
oki Semiconductor Co., Ltd.
International Classes:
G11C15/04; G11C15/00
Domestic Patent References:
| JP5101682A | ||||
| JP117782A |
Attorney, Agent or Firm:
Hisao Kobayashi
Kiyoshi Yasushima
Souji Sasaki
Noboru Omura
Takanashi Norio
Kiyoshi Yasushima
Souji Sasaki
Noboru Omura
Takanashi Norio