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Patent Searching and Data


Title:
ASSOCIATIVE MEMORY
Document Type and Number:
Japanese Patent JPH1064282
Kind Code:
A
Abstract:

To shorten a delivery time of data between words (PE) separated via a distance, by setting a clock multiplication circuit.

A clock system of the associative memory is impressed as it is to a word 11, a mask register 13, etc., by a clock distribution line 19 fed from a clock input part 18. In a shift mode, a clock from the clock input part 18 is passed through a clock multiplication circuit 20, multiplied N times (N is an optional integer not smaller than 2), and fed to a hit flag register 17. In other modes than the shift mode, the clock from the clock input part 18 is fed as it is. The clocks are switched by a control signal fed from a clock switch control input part 21.


Inventors:
IKENAGA TAKESHI
OGURA TAKESHI
Application Number:
JP23864196A
Publication Date:
March 06, 1998
Filing Date:
August 22, 1996
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G11C15/04; G11C15/00; (IPC1-7): G11C15/00
Attorney, Agent or Firm:
Nagao Tsuneaki