PURPOSE: To maintain high performance even in an environment in which the frequency of deletion is high by dividing the field of memory readout data in a storage device and adding a reverse predictor field, and adding decision devices corresponding to respective storage devices.
CONSTITUTION: The reverse predictor field 1a is added to N sets of storage devices 1; and N sets of decision devices 13 are added corresponding to the devices 1, and a probe counter 14, etc., are added to a probe decision circuit 5. When deleting operation is performed, an element which succeeded in being retrieved is erased firstly. Namely, 1 is written in a blank flag 1b, and the address of the element is inputted to a precedent address latch 10 to reset the circuit 14 to . Then, postcalculation is performed through an address latch 11, the devices 1, a hash address generator 2, the circuit 5, a phase compartor 8, field 1a, etc., to decide on a movable element, which is moved and erased. Thus, the field 1a, circuit 13, etc., are added to maintain the high performance even in an environment in which the frequency of deletion is high.
| JP4343859 | Semiconductor device |
| WO/2013/052688 | ENERGY EFFICIENT MEMORY WITH RECONFIGURABLE DECODING |
| JPS62117195 | CONTENT CALLING MEMORY |
NISHIDA KENJI
SHIMADA TOSHIO
