PURPOSE: To reduce the number of transistors and wirings used in a associative storage so as to reduce the chip size of the device by constituting an associative storage element by adding three transistors and one coincidence line to a static RAM element.

CONSTITUTION: A static RAM element 101 is constituted of 1st and 2nd inverters 102 and 103 and 1st and 2nd MOS transistors 104 and 105. The sources of 3rd and 4th MOS transistors 109 and 110 are respectively connected with the input and output of the 1st inverter 102 and gates of the transistors 109 and 110 are respectively connected with 1st and 2nd bit lines 107 and 108. The drains of the transistors 109 and 110 are commonly connected to each other. A 5th MOS transistor 111 is provided between the ground and a coincidence line 112 and its gate input is connected with the connecting point (drain) of the 3rd and 4th MOS transistors 109 and 110. In addition, a load resistance 113 is provided between the coincidence line 112 and a power source VDD. Since an associated storage element can be constituted in such way, the density of the storage element can be improved.