PURPOSE: To reduce signal delay time by half.

CONSTITUTION: Two D flip-flops 1A and 1B are provided to be driven by one clock signal CLK. A positive output Q of the preceding step flip-flop 1A is connected to a D input of the rear step flip-flop 1B, and an inverted output BA of the rear step flip-flop 1B is connected to a D input of the preceding step flipflop IA. For plural two-bit counters 10X, an inverted output BQ of the rear step flip-flop 1B in a preceding step two-bit counter 10X-1 is inputted as the clock signal of the respective flip-flops 1A and 1B in the rear step two-bit counter 10X, and the rear step two-bit counters 10X are serially connected so as to be driven.