PURPOSE: To minimize and economize a circuit by making (dividing) counter capacity for a transfer control provided on the output side of a buffer memory into the capacity portion of the buffer memory.

CONSTITUTION: A dividing counter 60 for the data transfer control provided on the output side of a buffer memory 40 satisfies a function as the capacity portion of a FIFO 40. For this, since the buffer memory 40 has the capacity of 16 bytes, the capacity of the dividing counter 60 is sufficient to be set at a 16 counter. Then, a value set before the starting of the data transfer of the 125 bytes is (7b)H in a counter 50, whereas, the counter 60 indicates lower-order 4 bits, that is, (b)H. For this, after the counter 60 indicates 0 in an END detecting part 70, a guard is applied not to notify the CPU 10 as far as it is not a transmission completing signal. Thus, the dividing counter 60 is sufficient to be the capacity in which the low-order bit end numeric value of the FIFO capacity can be written.