Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
ASYNCHRONOUS LOAD CIRCUIT
Document Type and Number:
Japanese Patent JPH04318708
Kind Code:
A
Abstract:

PURPOSE: To improve the count accuracy of a counter by outputting a carry output of the counter for a passing suppression time of an external load signal so as to attain periodic loading to the counter with an asynchronizing signal.

CONSTITUTION: An external input signal P is inputted to an external signal differentiating section 2, and since production of ±1 bit deviation in an external load signal EL outputted by using an internal clock CK inputted simultaneously is expected for each period of the signal P, when the signal EL is loaded to a counter 1, no periodic loading is caused. Thus, the time representing deviation of ±1 bit is inhibited by using a signal S generated by an external load suppression signal generator 3 and the load of the inhibited time is counted by using the internal clock CK and an internal signal CO carried and outputted for each prescribed count (n) is used to attain the periodic loading.


Inventors:
HIRAYAMA SEIICHIRO
SATO YOSHIKO
Application Number:
JP8643491A
Publication Date:
November 10, 1992
Filing Date:
April 18, 1991
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
FUJITSU LTD
International Classes:
H03K23/66; (IPC1-7): H03K23/66
Attorney, Agent or Firm:
Sadaichi Igita