To provide an asynchronous type counter circuit performing verification to a supply pass of a clock signal without complicating a circuit, and improving a failure detection rate.

This circuit is equipped with: a plurality of flip-flop circuits 11 for outputting an output signal corresponding to each bit, and a carrying signal; clock generation circuits 13 for generating an internal clock signal clk corresponding to a control signal SE for a scan test in each flip-flop circuit; and input signal generation circuits 12 for generating either of the carrying signal CS and an input signal SI for the scan test as an internal input signal, based on the control signal SE for the scan test. The clock generation circuits 13 is constituted so that an internal clock signal in the preceding stage is outputted as an internal clock signal in the present stage, when at least either of the carrying signal CS (enable signal En in the case of an initial stage) outputted from a flip-flop circuit in the preceding stage, and the control signal SE for the scan test is in an activated state.