To compensate the order of cells with less hardwares by reading the address information of the cells corresponding to time information from address buffers provided in output lines and reading the cells from a common memory corresponding to it.
The time information required for arrival is written in the cells arriving at input lines I1-Im and time buffers TB1-TBn for time sequentially holding the time information synchronized with absolute time are provided for the respective output lines O1-On. Write control parts W1-Wm extract the time information of the arriving cells and transfer it to the time buffers TB1-TBn. A threshold setting part TH compares the time information of the cells simultaneously arriving at the input lines I1-Im and sets the threshold of the time information. Read control parts R1-Rn read the time information of the time buffers TB1-TBn corresponding to the threshold., read the address information of the corresponding cells from the address buffers AB1-ABn and read the cells from the common memory M corresponding to it.
YAMANAKA NAOAKI
SHIOMOTO KOHEI
OKI EIJI
