PURPOSE: To provide a computer storage register architecture which allows sure atomic access for setting or clearing one or a plurality of specific bits in a plurality of bit registers.

CONSTITUTION: Many unique addresses 25 and 26 are assigned to a plurality of bit registers 10 and 11 and the first, second, and third addresses of the addresses are composed respectively of a reading address, a clearing address, and a setting address. An address decoder decodes the address designated to a register so that only the register can be accessed for related reading, clearing, or setting operation. The address corresponding to the data 27 having a binary pattern equivalent to the register position of zero logic and the specific bit position of a set or cleared register 10 or 11 is related to a set or cleared address. When the binary value equivalent to the position of the data related to a decoded address has logic of '1', the corresponding bit in the register is set or cleared. Otherwise, the bit remains unchanged.