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Title:
AUTO-ZERO INTERGRATING DEVICE
Document Type and Number:
Japanese Patent JPS61262981
Kind Code:
A
Abstract:

PURPOSE: To eliminate automatically an error output by holding the input offset voltage of an operational amplifier while the switch of an integrating capacitor is kept on and applying the held voltage to the non-reverse input terminal of the operational amplifire in the adverse polarity when said switch is turned off.

CONSTITUTION: The both ends of an integrating capacitor C1 are short-circuited by a switch SW4 is a reset auto-zero mode and the negative feedback is applied to an operational amplifier OP1. Thus the input offset voltage -VOS of the OP1 is kept at a point (a). Then switches SW1 and SW2 are set at a contact I in an integration mode with switches SW3 and SW4 opened respectively. Thus an auto-zero capacitor C2 is connected adversely between the non-reverse input terminal of the OP1 and an earth line. Then the voltage held by the C2 is applied in the adverse polarity to the non-reverse input terminal of the OP1. Thus the input offset voltage of the OP1 is cancelled and the potential at the point (a) is equal to the earth potential. In such a way, an error output is eliminated automatically and an integration output is obtained with high accuracy.


Inventors:
SHINODA YASUO
Application Number:
JP10647385A
Publication Date:
November 20, 1986
Filing Date:
May 17, 1985
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G06G7/186; H03F3/34; (IPC1-7): G06G7/186; H03F3/34
Domestic Patent References:
JPS6068476A1985-04-19
JPS59183470A1984-10-18
Attorney, Agent or Firm:
Masayoshi Misawa