Title:
AUTOMATIC CHECK METHOD AND SYSTEM FOR PRINTED CIRCUIT BOARD
Document Type and Number:
Japanese Patent JP2733202
Kind Code:
B2
Abstract:
PURPOSE: To provide a method and device which use an automatic optical check system for a printed circuit board that can generate allowance data by weighing each state of conversion data having at least three states and grouping adjacent pixels to show a defect when the sum of conversion weight of one group exceeds the threshold.
CONSTITUTION: A method and device which are used for a defect detection system of a printed circuit board(PCB) produce a reference data base image of the PCB which has allowable error of each PCB shape. The reference data base image can be characterized by an allowable error data base (50) in at least three states. Then each color is weighted and adjacent pixels are grouped into arrays, i.e., 'bins' in the data base (50). An error signal is generated when the bin pixel weight exceeds the threshold which is previously selected.
Inventors:
HAINTSU JOSEFU GAABAA
RONARUDO JEI SUTOREIYAA
BURUUSU ERU DEIBITSUDOSON
SUKOTSUTO PII SUNIIKA
JEEMUSU PII KOORAA
PIITAA EMU UORUSHU
DANA DABURYU SENIFU
RONARUDO JEI SUTOREIYAA
BURUUSU ERU DEIBITSUDOSON
SUKOTSUTO PII SUNIIKA
JEEMUSU PII KOORAA
PIITAA EMU UORUSHU
DANA DABURYU SENIFU
Application Number:
JP26298894A
Publication Date:
March 30, 1998
Filing Date:
October 26, 1994
Export Citation:
Assignee:
GAABAA SHISUTEMUSU CORP
International Classes:
G01B11/30; G01N21/956; G01R31/309; G06T1/00; G06T7/00; H05K3/00; (IPC1-7): G06T7/00; G01B11/30; H05K3/00
Domestic Patent References:
| JP4282442A |
Attorney, Agent or Firm:
Kunio Miura