Title:
AUTOMATIC ON-DIE FREQUENCY TUNING USING TUNABLE REPLICA CIRCUIT
Document Type and Number:
Japanese Patent JP2023093336
Kind Code:
A
Abstract:
To provide a device for optimizing the operation of multiple integrated circuits (ICs) operating in parallel.SOLUTION: In an ASIC1, a TRC210 is designed and configured to fail earlier than a processing engine's critical path and is used to reconfigure a PLL1 to maintain a stable stack voltage. The TRC210 tracks both the minimum and maximum delays and scales up or down the frequency of PLL1 accordingly. When the delay of TRC210 is below a lower threshold, the frequency of PLL1 is lowered. When the delay of TRC210 is above an upper threshold, the frequency of PLL1 is increased.SELECTED DRAWING: Figure 2
Inventors:
VIKRAM B SURESH
SANU K MATHEW
CHRISTOPHER SCHAEF
CHANDRA S KATTA
SHENG LONG
CHIN S PARK
SRINIVASAN RAJAGOPALAN
RAJU RAKHA
SANU K MATHEW
CHRISTOPHER SCHAEF
CHANDRA S KATTA
SHENG LONG
CHIN S PARK
SRINIVASAN RAJAGOPALAN
RAJU RAKHA
Application Number:
JP2022185646A
Publication Date:
July 04, 2023
Filing Date:
November 21, 2022
Export Citation:
Assignee:
INTEL CORP
International Classes:
G06F1/08; G06F1/04; H03L7/08
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Osamu Miyazaki
Naoki Fujimura
Tadahiko Ito
Osamu Miyazaki
Naoki Fujimura
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