Title:
AUTOMATIC EQUALIZER CIRCUIT
Document Type and Number:
Japanese Patent JP3168729
Kind Code:
B2
Abstract:
PURPOSE: To provide an automatic equalizer circuit that can employ an analog circuit and can automatically correct the tap coefficient in accordance with the distortion of an input signal.
CONSTITUTION: An input signal passes through a transversal filter consisting of a delay element, a coefficient multiplier and an adder and then inputted to the 1st and 2nd comparators 107 and 119 having the positive and negative threshold value respectively. The outputs of both comparators are added together by an adder 108, and the output of the adder of the transversal filter is subtracted from those added outputs by a subtractor 109. Thus a difference signal is obtained and multiplied by the output of each stage of the transversal filter by a multiplier 110. These results of multiplication are smoothed by the smoothing circuits 113, 114 and 115 for the change of coefficient of the coefficient multiplier. The error signals are equal to the continuous signals that have the effective value in all timings and therefore can be generated by an analog circuit.
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Inventors:
Masashi Tokunaga
Masafumi Shimoda
Masafumi Shimoda
Application Number:
JP27570092A
Publication Date:
May 21, 2001
Filing Date:
October 14, 1992
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G11B5/035; G11B20/10; H03H15/00; H03H17/00; H03H17/02; H03H17/06; H03H21/00; H04B3/14; (IPC1-7): H03H15/00; G11B5/035; G11B20/10; H03H17/02; H03H21/00; H04B3/14
Domestic Patent References:
| JP4817241A | ||||
| JP5454559A | ||||
| JP6075134A | ||||
| JP5922426A |
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)